Expert VHDL
Expert VHDL is an intensive 5-day advanced application class. It teaches engineers how to increase productivity by enhancing their knowledge of the VHDL language itself and its application for design and verification. Presented in two distinct course modules, Expert VHDL focuses on language and synthesis issues, design maintainability and re-use, structured verification environments and the latest techniques for verification - including an introduction to OVL/PSL and introductions to OSVVM and UVVM.
Description
What will you learn?
- A set of VHDL language features that go beyond what is taught on a basic training class
- A deeper understanding of how to apply VHDL language for design
- enabling you to troubleshoot VHDL simulation and synthesis problems with ease
- enabling code re-use
- The principles and details of how to approach the problem of design verification using VHDL
- How to structure and write large and complex VHDL structured verification environments
- The OSVVM and UVVM VHDL verification methodologies
Prerequisites
This is an advanced language and methodology training class. Prior attendance of the Doulos Comprehensive VHDL class (or equivalent) is required, and at least 6 months of 'live' project experience using VHDL is strongly recommended. Delegates attending the Expert Design module must have knowledge and experience of register transfer level coding and synthesis using VHDL.