VHDL for Designers
prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices. Delegates targeting FPGAs will take away a flexible project infrastructure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects.
Description
- The VHDL language concepts and constructs essential for FPGA design
- How to write VHDL for effective RTL synthesis
- How to target VHDL code to an FPGA device architecture
- How to write simple VHDL test benches
- The tool flow from VHDL through simulation, synthesis and place-and-route
- How to write high quality VHDL code that reflects best practice in the industry
Introduction
The scope and application of VHDL • Design and tool flow • FPGAs • The VHDL world
Getting Started
The basic VHDL language constructs • VHDL source files and libraries • The compilation procedure • Synchronous design and timing constraints
FPGA Design Flow (Practical exercises using a hardware board)
Simulation • Synthesis • Place-and-Route • Device programming
Design Entities
Entities and Architectures • Std_logic • Signals and Ports • Concurrent assignments • Instantiation and Port Maps • The Context Clause
Processes
The Process statement • Sensitivity list versus Wait • Signal assignments and delta delays • Register transfers • Default assignment • Simple Testbenches
Synthesising Combinational Logic
If statements • Conditional signal assignments and Equivalent process • Transparent latches • Case statements • Synthesis of combinational logic
Types
VHDL types • Standard packages • Integer subtypes • Std_logic and std_logic_vector • Slices and concatenation • Integer and vector values
Synthesis of Arithmetic
Arithmetic operator overloading • Arithmetic packages • Mixing integers and vectors • Resizing vectors • Resource sharing
Synthesising Sequential Logic
RISING_EDGE • Asynchronous set or reset • Synchronous inputs and clock enables • Synthesisable process templates • Implying registers
FSM Synthesis
Enumeration types • VHDL coding styles for FSMs • State encoding • Unreachable states and input hazards
Memories
Array types • Modelling memories • IP Generators • Instantiating generated components • Implementing ROMs
Basic TEXTIO
TEXTIO • READ and WRITE • Using TEXTIO for testbench stimulus and outputs • STD_LOGIC_TEXTIO